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The figure shows the high-frequency capacitance-voltage (C-V) characteristics of a Metal/SiO2 /silicon (MOS) capacitor having an area of 1x10-4 cm2. Assume that the permitivities (εoεr) of silicon and SiO2 are 1x10-12 F/cm and 3.5x10-13 F/cm respectively.
[1] The gate oxide thickness in the MOS capacitor is: [2 marks]
(A) 50 nm
(B) 143 nm
(C) 350 nm
(D) 1 µm[2] The maximum depletion layer width in silicon is [2 marks]
(A) 0.143 µm
(B) 0.857 µm
(C) 1 µm
(D) 1.143 µm[3] Consider the following statements about the C-V characteristics plot:
S1: The MOS capacitor has an n-type substrate.
S2: If positive charges are introduced in the oxide, the C-V plot will shift to the
left.
Then which of the following is true? [2 marks]
(A) Both S1 and S2 are true
(B) S1 is true and S2 is false
(C) S1 is false and S2 is true
(D) Both S1 and S2 are falseasked in Electronics and Communication Engineering, 2007
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